View EL8178FWZ-T7_6318456.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn7504.7 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004-2008. all rights reserved. all other trademarks mentioned are the property of their respective owners. el8178 micropower single s upply rail-to-rail input-output (rrio) precision op amp the el8178 is a precision low power, operational amplifier. the device is optimized for single supply operation between 2.4v to 5.5v. this enables operation from one lithium cell or two ni-cd batteries. the input range includes both positive and negative rail. for power sensitive applications, the el8178 has and en pin that will shut the device down and reduce the supply current to 3a typ. in the ac tive state, the el8178 draws minimal supply current (55a) while meeting excellent dc-accuracy, noise, and out put drive specifications. features ? typical 55a supply current ? 250v max offset voltage ? typical 1pa input bias current ? 266khz gain-bandwidth product ? single supply operation between 2.4v to 5.5v ? rail-to-rail input and output ? ground sensing ? output sources and si nks 26ma load current ? pb-free (rohs compliant) applications ? battery- or solar-powered systems ? 4ma to 20ma current loops ? handheld consumer products ? medical devices ? thermocouple amplifiers ? photodiode pre-amps ? ph probe amplifiers ordering information part number (note 1) part marking package (pb-free) pkg. dwg. # EL8178FWZ-T7* bbwa 6 ld sot-23 mdp0038 EL8178FWZ-T7a* bbwa 6 ld sot-23 mdp0038 el8178fsz 8178fsz 8 ld so mdp0027 el8178fsz-t7* 8178fsz 8 ld so mdp0027 *please refer to tb347 for detai ls on reel specifications. note: 1. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. pinouts el8178 (6 ld sot-23) top view el8178 (8 ld so) top view 1 2 3 6 4 5 +- out v- in+ v+ en in- 1 2 3 4 8 7 6 5 - + nc in- in+ en v+ out v- nc data sheet may 14, 2008 f o r a p o s s i b l e s u b s t i t u t e p r o d u c t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c o b s o l e t e p r o d u c t
2 fn7504.7 may 14, 2008 absolute maxi mum ratings (t a = +25c) thermal information supply voltage (v s ) and pwr-up ramp rate . . . . . . . 5.75v, 1v/s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v current into in+, in-, and en . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma input voltage . . . . . . . . . . . . . . . . . . . . . . . . . v- - 0.5v to v+ + 0.5v esd tolerance human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v thermal resistance (typical, note 2) ja (c/w) 6 ld sot-23 package . . . . . . . . . . . . . . . . . . . . . . . 230 8 ld so package . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ambient operating temperature range . . . . . . . . -40c to +125c storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v+ = 5v, v- = 0v, v cm = 2.5v, v o = 2.5v, t a = +25c unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. parameter description test conditions min (note 3) typ max (note 3) unit v os input offset voltage -250 50 250 v -450 450 v long term input offset voltage stability 3v/mo input offset drift vs temperature 1.1 v/c i b input bias current -25 1 25 pa -600 600 pa i os input offset current -30 10 30 pa -600 600 pa e n input noise voltage peak-to-peak f = 0.1hz to 10hz 2.8 v p-p input noise voltage density f o = 1khz 48 nv/ hz i n input noise current density f o = 1khz 0.15 pa/ hz cmir input voltage range guaranteed by cmrr test 0 5 v cmrr common-mode rejection ratio v cm = 0v to 5v 80 100 db 75 db psrr power supply rejection ratio v s = 2.4v to 5.5v 80 100 db 80 db a vol large signal voltage gain v o = 0.5v to 4.5v, r l = 100k to (v+ + v-)/2 100 400 v/mv 100 vmv v os time ------------------ v os t --------------- - el8178
3 fn7504.7 may 14, 2008 v out maximum output voltage swing sot-23/so-8 v ol ; output low, r l = 100k to (v+ + v-)/2 3 10 mv v ol ; output low, r l = 1k to (v+ + v-)/2 130 250 mv 350 mv v oh ; output high, r l = 100k to (v+ + v-)/2 4.994 4.9975 v v oh ; output high, r l = 1k to (v+ + v-)/2 4.750 4.875 v 4.7 v sr slew rate 0.10 0.15 0.19 v/s 0 . 07 0 . 25 v/s gbwp gain bandwidth product f o = 100khz 266 khz i s(on) supply current, enabled sot-23/so-8 35 55 75 a 30 85 a i s(off) supply current, disabled 3 5 a i sc + short circuit output sourcing current r l = 10 to opposite supply 23 31 ma 18 ma i sc - short circuit output sinking current r l = 10 to opposite supply 20 26 ma 15 ma v s supply voltage guaranteed by psrr 2.4 5.5 v 2.4 5.5 v v inh en pin high level 2 v v inl en pin low level 0.8 v i enh en pin input current v en = 5v 0.25 0.8 2.5 a i enl en pin input current v en = 0v -0.5 +0.5 a note: 3. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications v+ = 5v, v- = 0v, v cm = 2.5v, v o = 2.5v, t a = +25c unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter description test conditions min (note 3) typ max (note 3) unit el8178
4 fn7504.7 may 14, 2008 typical performance curves v s = 2.5v, t a = +25c, unless otherwise specified figure 1. unity gain frequency response at various supply voltages figure 2. frequency response at various closed loop gains figure 3. supply current vs supply voltage figur e 4. input offset voltage vs output voltage figure 5. input offset voltage vs common-mode input voltage figure 6. open loop gain and phase vs frequency (r l = 1k ) -3 -2 -1 0 1 1k 10k 100k 1m v s = 1.0v v s = 2.5v v s = 1.25 gain (db) frequency (hz) r l 10k v out = 0.2v p-p -20 -10 0 10 20 30 40 50 60 70 80 1 10 100 1k 10k 100k 1m 10m frequency (hz) gain (db) gain = 200 gain = 1k gain = 500 gain = 100 gain = 10 gain = 1 gain = 5 gain = 2 r l 10k v out = 0.2v p-p 2.0 3 4.0 5.5 0 supply voltage (v) supply current (a) 2.5 10 20 50 60 30 40 3.5 5.0 4.5 -0.5 5.5 -200 output voltage (v) input offset voltage (v) -100 0 200 100 0.5 1.5 2.5 3.5 4.5 a v = -1 v cm = v dd /2 -0.5 5.5 -250 common-mode input voltage (v) normalized input offset voltage (v) -150 -50 250 150 0.5 1.5 2.5 3.5 4.5 50 -20 gain (db) 0 20 80 100 40 60 10 10 k 1m frequency (hz) 100 phase shift () 0 45 90 135 180 100 k 1 k phase gain el8178
5 fn7504.7 may 14, 2008 figure 7. open loop gain and phase vs frequency (r l = 100k ) figure 8. cmrr vs frequency figure 9. psrr vs frequency figure 10. input voltag e and current noise vs frequency figure 11. 0.1hz to 10hz input voltage noise typical performance curves v s = 2.5v, t a = +25c, unless otherwise specified (continued) -10 0 10 20 30 40 50 60 70 80 90 100 10 100 1k 10k 100k 1m frequency (hz) gain (db) 180 135 90 gain phase phase shift () -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 10 frequency (hz) cmrr (db) 0 v cm = 1v p-p r l = 100k 10 100 1k 10k 100k 1m a v = +1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1k 10k 100k frequency (hz) psrr (db) +psrr -psrr v s = 1v p-p r l = 100k a v = +1 1m 1 10 100 1000 1 10 100 1k 10k 100k frequency (hz) voltage noise (nv/ hz ) 0.1 1 10 100 current noise (pa/ hz ) current voltage time (1s/div) voltage noise (500nv/div) 2.8v p-p el8178
6 fn7504.7 may 14, 2008 figure 12. vos drift (sot-23 package) vs time figure 13. v os drift (soic package) vs time figure 14. enabled supply current vs temperature, v s = 2.5v figure 15. disabled supply current vs temperature, v s = 2.5v figure 16. v os vs temperature, v s = 2.5v figure 17. v os vs temperature, v s = 1.2v typical performance curves v s = 2.5v, t a = +25c, unless otherwise specified (continued) -15 -10 -5 0 5 10 15 20 0 500 1000 1500 time (hours) v os drift (v) 1800 -12 -7 -2 3 8 13 18 0 500 1000 1500 v os drift (v) time (hours) 35 40 45 50 55 60 65 70 75 -40 -20 0 20 40 60 80 100 120 temperature (c) current (ma) median min max n = 1500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 -20 0 20 40 60 80 100 120 temperature (c) current (ma) median min max n = 1500 -400 -300 -200 -100 0 100 200 300 400 -40 -20 0 20 40 60 80 100 120 temperature (c) v os (v) median min max n = 1500 -800 -600 -400 -200 0 200 400 600 800 v os (v) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 el8178
7 fn7504.7 may 14, 2008 figure 18. i bias+ vs temperature, v s = 2.5v figure 19. i bias- vs temperature, v s = 2.5v figure 20. i os vs temperature, v s = 2.5v figure 21. a vol vs temperature, r l = 100k, v o = 2v @ v s = 2.5v figure 22. cmrr vs temperature, v+ = 2.5v, 1.5v figure 23. psrr vs temperature 1.5v to 2.5v typical performance curves v s = 2.5v, t a = +25c, unless otherwise specified (continued) 0 50 100 150 200 250 -40 -20 0 20 40 60 80 100 120 temperature (c) i bias + (pa) median min max n = 5000 0 50 100 150 200 250 300 350 400 450 -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 5000 i bias - (pa) -50 0 50 100 150 200 250 300 -40 -20 0 20 40 60 80 100 120 temperature (c) i os (pa) median min max n = 5000 160 210 260 310 360 410 460 510 a vol (v/mv) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 80 85 90 95 100 105 110 115 120 125 130 cmrr (db) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 85 90 95 100 105 110 115 120 125 130 psrr (db) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 el8178
8 fn7504.7 may 14, 2008 figure 24. v out high vs temperature, v s = 2.5v, r l =1k figure 25. v out high vs temperature, v s = 2.5v, r l =100k figure 26. v out low vs temperature, v s = 2.5v, r l =1k figure 27. v out low vs temperature, v s = 2.5v, r l =100k typical performance curves v s = 2.5v, t a = +25c, unless otherwise specified (continued) 4.84 4.85 4.86 4.87 4.88 4.89 4.90 v out (v) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 4.9964 4.9966 4.9968 4.9970 4.9972 4.9974 4.9976 4.9978 4.9980 4.9982 4.9984 v out (v) -40-200 20406080100120 temperature (c) median min max n = 1500 100 110 120 130 140 150 160 170 180 190 v out (mv) -40-200 20406080100120 temperature (c) median min max n = 1500 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v out (mv) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 el8178
9 fn7504.7 may 14, 2008 application information introduction the el8178 is a rail-to-rail input and output (rrio), micropower, precision, single supply op amp with an enable feature. this amplifier is de signed to operate from single supply (2.4v to 5.5v) or dual supply (1.2v to 2.75v) while drawing only 55a of supply current.the device achieves rail-to-rail input and output o peration while eliminating the drawbacks of many conventional rrio op amps. rail-to-rail input the pfet input stage of the el8178 has an input common-mode voltage range that includes the negative and positive supplies without in troducing offset errors or degrading performance like some existing rail-to-rail input op amps. many rail-to-rail input stages use two differential input pairs: a long-tail pnp (or pfet) and an npn (or nfet). severe penalties result from using this topology. as the input signal moves from one supply rail to the other, the op amp switches from one inpu t pair to the other causing changes in input offset voltage and an undesired change in the input offset current?s magnitude and polarity. the el8178 achieves rail-to-rail input performance without sacrificing important precision specifications and without degrading distortion performance. the el8178's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. rail-to-rail output a pair of complementary mosfet devices achieve rail-to-rail output swing. the nmos sinks current to swing the output in the negative direction, while the pmos sources current to swing the output in the positiv e direction. the el8178 with a 100k load swings to within 3mv of the supply rails. results of overdriving the output caution should be used when overdriving the output for long periods of time. overdriving the output can occur in three ways: 1. the input voltage times the gain of the amplifier exceeds the supply voltage by a large value. 2. the output current required is higher than the output stage can deliver. 3. operating the device in slew rate limit. these conditions can result in a shift in the input offset voltage (v os ) as much as 1v/hr of exposure u nder these conditions. enable/disable feature the el8178 features an active low en pin that when pulled up to at least 2v, disables the output and drops the i cc to a 3a. the en pin has an internal pull-down, so an undriven pin pulls to the negative rail, thereby enabling the op amp by default. for applications where the en pin is not being used, it is recommended that the en pin be permanently tyed to ground. the high impedance output during disable allows for connecting multiple el8178s together to implement a mux amp. the outputs are connected together and activating the appropriate en pin selects the desired channel. if utilizing non-unity gain op amp configurations, then the loading pin descriptions so pin number sot-23 pin number pin name equivalent circuit description 1 nc no internal connection 2 4 in- circuit 1 amplifier?s inverting input 3 3 in+ circuit 1 amplifier?s non-inverting input 4 2 v- circuit 4 negative power supply 5 nc no internal connection 6 1 out circuit 3 amplifier?s output 7 6 v+ circuit 4 positive power supply 85en circuit 2 amplifier?s enable pin with internal pull-down; logic ?1? selects the disabled state; logic ?0? selects the enabled state. en out circuit 3 circuit 2 capacitively coupled esd clamp circuit 4 v + v + v + v - v - v - in- v + v - circuit 1 in+ el8178
10 fn7504.7 may 14, 2008 effects of the disabled amplifiers? feedback networks must be considered when evaluating the active amplifier?s performance in mux amp configurations. note that feed through from the in+ to in- pins occurs on any mux amp disabled channel where the input differential voltage exceeds 0.5v (e.g., active channel v out = 1v, while disabled channel v in = gnd), so the mux implementation is best suited for small signal applications. in any application where two or more amplifier outputs are muxed, use series in+ resistors, or large value r f s in each amplifier to keep the feed through current low enough to minimize the impact on the active channel. see ?usage implications? on page 10 for more details. in+ and in- input protection in addition to esd protection diodes to each supply rail, the el8178 has additional back-to-back protection diodes across the differential input terminals. if the magnitude of the differential input voltage exceeds the diode?s v f , then one of these diodes will conduct. for elevated temperatures, the leakage of the protection di odes (see circuit 1 in ?pin descriptions? on page 9) increases, resulting in the increase in i bias , as seen in figures 18 and 19. usage implications if the input differential voltage is expected to exceed 0.5v, an external current limiting resistor must be used to ensure the input current never exceeds 5ma. for noninverting unity gain applications, the current limiting can be via a series in+ resistor, or via a feedback resistor of appropriate value. for other gain configurations, the series in+ resistor is the best choice, unless the feedback (r f ) and gain setting (r g ) resistors are both sufficiently large to limit the input current to 5ma. large differential input voltages can arise from several sources: 1. during open loop (comparator) operation. the in+ and in- input voltages don?t track. 2. when the amplifier is disabled but an input signal is still present. an r l or r g to gnd keeps the in- at gnd, while the varying in+ signal creates a differential voltage. mux amp applications are similar, except that the active channel v out determines the voltage on the in- terminal. 3. when the slew rate of the input pulse is considerably faster than the op amp?s slew rate. if the v out can?t keep up with the in+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. to avoid this issue, keep the input slew rate below 0.2v/s, or use appropriate current limiting resistors. large (>2v) differential input voltages can also cause an increase in disabled i cc . en i nput protection the en input has internal esd pr otection diodes to both the positive and negative supply rails , limiting the input voltage range to within one diode beyond the supply rails (see ?circuit 2? diagram on page 9). if the input voltage is expected to exceed v+ or v-, then an external series resistor should be added to limit the current to 5ma. output current limiting the el8178 has no internal current -limiting circuitry. if the output is shorted, it is poss ible to exceed the ?absolute maximum rating? for ?operating junction temperature?, potentially resulting in the destruction of the device. power dissipation it is possible to exceed the +150c maximum junction temperature (t jmax ) under certain load and power-supply conditions. it is therefor e important to calculate t jmax for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. these parameters are related in equation 1: where pd max is calculated using equation 2: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of the amplifier ?v s = supply voltage ?i max = maximum supply current of the amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance t jmax t max ja xpd max () + = (eq. 1) pd max v s i smax v s ( - v outmax ) v outmax r l ---------------------------- + = (eq. 2) el8178
11 fn7504.7 may 14, 2008 proper layout maximizes precision to achieve the optimum levels of high input impedance (i.e., low input currents) and low offset voltage, care should be taken in the circuit board layout. the pc board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. when input leakage current is a paramount concern, the use of guard rings around the amplif ier inputs will further reduce leakage currents. figure 28 shows a guard ring example for a unity gain amplifier that us es the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. the guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. for further reduction of leakage currents, mount components to the pc board using teflon standoffs.. typical applications a general-purpose combination ph probe has extremely high output impedance typically in the range of 10g to 12g . low loss and expensive teflon cables are often used to connect the ph probe to the meter electronics. figure 29 details a low-cost alternative solution using the el8178 and a low-cost coax cable. the el8178 pmos high impedance input senses the ph probe output signal and buffers it to drive the coax cable. its rail-to-rail input nature also eliminates the need for a bias resistor network required by other amplifiers in the same application. thermocouples are the most popular temperature sensing devices because of their low cost, interchangeability, and ability to measure a wide range of temperatures. in figure 30, the el8178 converts the differential thermocouple voltage into single-ended signal with 10x gain. the el8178's rail-to-rail input characteristic allows the thermocouple to be biased at ground and permits th e op amp to operate from a single 5v supply. in v+ figure 28. guard ring example for unity gain amplifier high impedance input - + 3v + v+ v- el8178 coax general purpose combination ph probe figure 29. ph probe amplifier - + 5v + v+ v- el8178 k type thermocouple 10k r 3 10k r 2 r 4 100k r 1 100k 410 v/c figure 30. thermocouple amplifier el8178
12 fn7504.7 may 14, 2008 el8178 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7504.7 may 14, 2008 el8178 sot-23 package family e1 n a d e 4 3 2 1 e1 0.15 d c 2x 0.20 c 2x e b 0.20 m d c a-b b nx 6 2 3 5 seating plane 0.10 c nx 1 3 c d 0.15 a-b c 2x a2 a1 h c (l1) l 0.25 0 +3 -0 gauge plane a mdp0038 sot-23 package family symbol millimeters tolerance sot23-5 sot23-6 a 1.45 1.45 max a1 0.10 0.10 0.05 a2 1.14 1.14 0.15 b 0.40 0.40 0.05 c 0.14 0.14 0.06 d 2.90 2.90 basic e 2.80 2.80 basic e1 1.60 1.60 basic e 0.95 0.95 basic e1 1.90 1.90 basic l 0.45 0.45 0.10 l1 0.60 0.60 reference n 5 6 reference rev. f 2/07 notes: 1. plastic or metal protrusions of 0.25mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. this dimension is measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. index area - pin #1 i.d. will be located within the indicated zone (sot23-6 only). 6. sot23-5 version has no center lead (shown as a dashed line).

▲Up To Search▲

Price & Availability of EL8178FWZ-T7

	To Download EL8178FWZ-T7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .